Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique

In recent years, low power consumption has been an important consideration for the design of system since there is a high demand for consumer electronics such as cellphones for a longer battery life. This paper presents the simulation of half adder, half subtractor, full adder, and the full subtractor. The presented circuit contains NAND gates combining the NMOS and PMOS. These CMOS circuitries has the advantage of lower voltage, lower power consumption, and higher energy efficiency. The NMOS and PMOS were bridge together to produce the desired output. This design provides the CMOS half adder, half subtractor, full adder, and full subtractor using the Tanner EDA software tool. The complete CMOS circuit schematic are described in this paper. The design methods and principles are described thereafter. Simulations have been done with the use of the Tanner EDA tool in a CMOS technology standard and response output was verified comparing the obtained waveform along with its truth table. In comparison with conventional logic truth table, T-Spice output simulation matches with theoretical expectations. Keywords—Adders, CMOS, logic gates, NMOS, PMOS, Spice, subtractors, Tanner EDA


INTRODUCTION
In digital electronics, logic gate is an electronic device that performs Boolean logic, wherein the inputs and outputs are in terms of binary numbers. The adders and subtractors of two or more binary digits can be designed through the combinational Boolean logic circuits. Nowadays, low power consumption is an important consideration in designing a system [1][2]. In the design of very large-scale integration or VLSI, the low power consumption of the system is increasing in demand. VLSI has applied in engineering applications such as microcontrollers, communications, a digital image processing, microprocessors, digital signal processing, among others [3][4]. In case that the system is not power efficient, it may consume more power and the system may suffer from working in a higher temperature, lower economic battery life, and additional operation costs. In effect, it may have an adverse influence in the performance of the system and its economic life.
In recent years, the CMOS or complementary metal oxide semiconductor field effect transistors is steadily gaining more attention from the research community that is associated in the design of the VLSI. It has been extensively used in integrated circuit memories, microcontrollers, microprocessors, etc. [4] as an alternative solution for smaller power consumption of system. It has an advantages of higher noise margin, consumes low power, and ease of design [5]. It uses symmetrical pairs and complementary pairs of n-type and p-type, which are the NMOS and PMOS, respectively for digital electronics such as the Boolean logic functions applications.
[6] presented a paper on full adder using a CMOS technology, that is good for low power consumption. Gayathri, et al. [7] developed a 1-bit full adder using gate diffusion input for static leakage reduction. Kumar and Goyal [8] presented a study of several full adders with the aid of Tanner EDA software. Sharma and Sharma [9] studied the 1bit half subtractor using CMOS technology by means of DSCH and Microwind software tools. Monikashri, et al. [10], Rajni and Dhimari [11], Kumar, et al. [12] have studied the 1bit full subtractor using the CMOS technology by means of a software tool which is Tanner EDA.
The use of CMOS technology can be further applied to a diversified scientific and engineering problems including the minimization of a PCB area in electronic circuits [13] [14], the power electronics and motor drives [15] [16] [17], chip to chip communication [18], robotic [ In this paper, a CMOS 1-bit half adder, half subtractor, full adder, and full subtractor is presented using the Tanner EDA software. An assessment is made to verify the performance of the circuit through different logic function input combination and to check the voltage levels output signals. The adders and subtractors are indispensable in digital electronic circuits and logic gates, and these are incorporated in integrated circuits. This paper is organized as follows. Section II presents the discussion of this project. Simulation results are presented and discussed under Section III. Finally, the conclusion is given in Section IV.

A. General Flowchart
The block diagram shown in Figure 1 illustrate the design process of the system. The schematic circuit was designed in the Tanner EDA software using PMOS and NMOS available in the library. The circuit design will be validated through a T-Spice simulation available in the Tanner EDA. If in case the simulation output response is not good or not satisfactory, then the circuit design will be re-check and troubleshoot. If in case that the response is in good agreement with theoretical expectations, then simulation will be halted, and all data will be gathered and saved. The overall block flowchart during the design process is illustrated in Figure 1 using Tanner EDA.   Figure 2 presents a simple circuitry NAND gate using the cascaded PMOS and NMOS, this serves as the building block in constructing the adders and subtractors in this paper. Figure 3 shows the half adder circuit using NAND gates. The circuit was composed of twenty transistors to complete the half adder circuit. It shows the connection of the PMOS and NMOS that was bridged together to produce the half adder circuit while Figure 4 shows the schematic diagram of half subtractor using NAND gates. Buffer was incorporated at the output to produce a more stable output response.

B. Circuit Schematics
The circuits uses PMOS and NMOS to design half adder and half subtractor and full subtractor. The circuit designed used NAND gates to produce the desired outputs, and with the help of the buffer, the output waveforms have been achieved which is more stable than without using a buffer in the design. Figure 5 illustrates the schematic diagram of the full adder using NAND gates. The PMOS and NMOS are the transistors that were used to create a full adder circuit using CMOS and with the help of truth table, the researchers have verified the results are correct.
Lastly, Figure 6 presents the circuit diagram of a CMOS full subtractor using NAND gates. Just like with the first three diagrams, it also uses PMOS and NMOS to create the NAND gate. Buffers were used to obtain a stable output response as compared to without using a buffer in designed circuit.

III. SIMULATION RESULTS
The figure below first and second graph in Figure 7 shows the general result of half adder in accordance with a two logic inputs (i.e., 0011 and 0101). The third and fourth graph shows the carry and sum of the half adder system.    Figure 8 depicts the input and the output results of the half subtractor. The first and second graphs are the inputs while the third and fourth graphs are the borrow and the difference respectively.
While Figure 9 depicts the simulation results of the full adder according with the inputs of 00001111, 00110011 and 01010101. The fourth and fifth graph are the carry and sum.  Figure 10 presents the result of a full subtractor that was implemented in the Tanner EDA software tool. The first three graphs show the inputs 00001111, 00110011 and 01010101, while the fourth and fifth graphs below on it, are the results.

IV. CONCLUSION
In this paper, the researchers have designed and tested the functionalities of the half adder, the half subtractor, the full adder, and the full subtractor using the Tanner EDA software tool. The design principles of logic circuits using NAND Gates had been applied to create a CMOS half and full adders also with half and full subtractors circuit through PMOS and NMOS. Simulation studies have been carried out to verify the effectiveness of the proposed scheme. Results reveal that the CMOS circuit design enables the logic function of half adder, half subtractor, the full adder, and full subtractor effectively.
The circuit design is universal and may readily applied to real world engineering applications. Future work will focus on prototype development and applications of the present work.