BELTRAN JR., A. A.; NONES, K.; SALANGUIT, R. L.; SANTOS, J. B.; SANTOS, J. M. R.; DIZON, K. J. Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique. Journal of Robotics and Control (JRC), [S. l.], v. 2, n. 4, p. 252–257, 2021. DOI: 10.18196/jrc.2487. Disponível em: https://journal.umy.ac.id/index.php/jrc/article/view/8832. Acesso em: 18 sep. 2025.