Aplikasi Perancang Abstraksi Verilog Mesin Keadaan Terbatas Otomatis
DOI:
https://doi.org/10.18196/st.v24i2.12863Keywords:
Control unit, FSM, VerilogAbstract
Saat ini, hampir semua perangkat elektronik menggunakan prosesor di dalamnya. Dalam sebuah prosesor, terdapat bagian control unit yang berfungsi mengatur operasi dari komponen-komponen di dalam prosesor. Control unit merupakan sebuah mesin keadaan terbatas atau disebut finite state machine (FSM). Rangkaian FSM dapat disintesis secara manual ataupun secara otomatis menggunakan bahasa abstraksi Verilog. Dalam penelitian ini, dibuat sebuah aplikasi yang dapat membantu pengguna merancang FSM dan selanjutnya menyimpannya dalam format Verilog. Aplikasi yang dibuat secara fungsional dapat berjalan dengan kesesuaian 100% dan mampu untuk membuat rancangan Verilog untuk FSM dengan berbagai model dan teknik pengkodean state. Simulasi modul Verilog yang dihasilkan juga sesuai dengan spesifikasi rangkaian FSM yang dirancang.References
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