Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique

Angelo A. Beltran Jr., Kristina Nones, Reina Louise Salanguit, Jay Bhie Santos, Jose Maria Rei Santos, Keith Joseph Dizon

Abstract


In recent years, low power consumption has been an important consideration for the design of system since there is a high demand for consumer electronics such as cellphones for a longer battery life. This paper presents the simulation of half adder, half subtractor, full adder, and the full subtractor. The presented circuit contains NAND gates combining the NMOS and PMOS. These CMOS circuitries has the advantage of lower voltage, lower power consumption, and higher energy efficiency. The NMOS and PMOS were bridge together to produce the desired output. This design provides the CMOS half adder, half subtractor, full adder, and full subtractor using the Tanner EDA software tool. The complete CMOS circuit schematic are described in this paper. The design methods and principles are described thereafter. Simulations have been done with the use of the Tanner EDA tool in a CMOS technology standard and response output was verified comparing the obtained waveform along with its truth table. In comparison with conventional logic truth table, T-Spice output simulation matches with theoretical expectations.


Keywords


Adders, CMOS, Logic Gates, NMOS, PMOS, Spice, Subtractors, Tanner EDA

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References


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DOI: https://doi.org/10.18196/jrc.2487

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